4. Cache Organization and Coherency
4.1 Primary Instruction Cache
The processor has an on-chip 32-Kbyte primary instruction cache (also referred to simply as the instruction cache), which is a subset of the secondary cache. Organization of the instruction cache is shown in Figure 4-1.
The instruction cache has a fixed block size of 16 words and is two-way set associative with a least-recently-used (LRU) replacement algorithm.*1
The instruction cache is indexed with a virtual address and tagged with a physical address.
Figure 4-1 Organization of Primary Instruction Cache
Each instruction cache block is in one of the following two states:
An instruction cache block can be changed from one state to the other as a result of any one of the following events:
- a primary instruction cache read miss
- subset property enforcement
- any of various CACHE instructions
- external intervention exclusive and invalidate requests
These events are illustrated in Figure 4-2, which shows the primary instruction cache state diagram.
Figure 4-2 Primary Instruction Cache State Diagram
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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